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| STL9NK30Z N-CHANNEL 300V - 0.36 - 9A PowerFLATTM Zener-Protected SuperMESHTMPower MOSFET TYPE STL9NK30Z s s s s s s s VDSS 300 V RDS(on) < 0.4 ID (1) 9A Pw (1) 75 W TYPICAL RDS(on) = 0.36 EXTREMELY HIGH dv/dt CAPABILITY IMPROVED ESD CAPABILITY 100% AVALANCHE RATED GATE CHARGE MINIMIZED VERY LOW INTRINSIC CAPACITANCES VERY GOOD MANUFACTURING REPEATIBILITY PowerFLATTM(5x5) (Chip Scale Package) DESCRIPTION The SuperMESHTM series is obtained through an extreme optimization of ST's well established stripbased PowerMESHTM layout. In addition to pushing on-resistance significantly down, special care is taken to ensure a very good dv/dt capability for the most demanding applications. Such series complements ST full range of high voltage MOSFETs including revolutionary MDmeshTM products. INTERNAL SCHEMATIC DIAGRAM APPLICATIONS LIGHTING s IDEAL FOR OFF-LINE POWER SUPPLIES, ADAPTORS AND PFC s ORDERING INFORMATION SALES TYPE STL9NK30Z MARKING L9NK30Z PACKAGE PowerFLATTM (5x5) PACKAGING TAPE & REEL August 2002 1/8 STL9NK30Z ABSOLUTE MAXIMUM RATINGS Symbol VDS VDGR VGS ID (2) IDM (2) PTOT (2) PTOT (1) VESD(G-S) dv/dt (4) Tstg Tj Parameter Drain-source Voltage (VGS = 0) Drain-gate Voltage (RGS = 20 k) Gate- source Voltage Drain Current (continuous) at TC = 25C (Steady State) Drain Current (continuous) at TC = 100C Drain Current (pulsed) Total Dissipation at TC = 25C (Steady State) Total Dissipation at TC = 25C (Steady State) Derating Factor (2) Gate source ESD(HBM-C=100pF, R=1.5K) Peak Diode Recovery voltage slope Storage Temperature Max. Operating Junction Temperature Value 300 300 30 9 5.6 36 2.5 75 0.6 3000 4.5 -55 to 150 Unit V V V A A A W W W/C V/ns V/ns C THERMAL DATA Symbol Rthj-F Note: 1. 2. 3. 4. Parameter Thermal Resistance Junction-Foot (Drain) Max. 1.6 50 Unit C/W C/W Rthj-amb (2) Thermal Resistance Junction-ambient The value is rated according to Rthj-F. When Mounted on FR-4 Board of 1inch2, 2 oz Cu Pulse width limited by safe operating area ISD< 9A, di/dt<300A/s, VDD Symbol IAR EAS Parameter Avalanche Current, Repetitive or Not-Repetitive (pulse width limited by Tj max) Single Pulse Avalanche Energy (starting Tj = 25 C, ID = IAR, VDD = 50 V) Max Value 9 155 Unit A mJ GATE-SOURCE ZENER DIODE Symbol BVGSO Parameter Gate-Source Breakdown Voltage Test Conditions Igs= 1mA (Open Drain) Min. 30 Typ. Max. Unit V PROTECTION FEATURES OF GATE-TO-SOURCE ZENER DIODES The built-in back-to-back Zener diodes have specifically been designed to enhance not only the device's ESD capability, but also to make them safely absorb possible voltage transients that may occasionally be applied from gate to source. In this respect the Zener voltage is appropriate to achieve an efficient and cost-effective intervention to protect the device's integrity. These integrated Zener diodes thus avoid the usage of external components. 2/8 STL9NK30Z ELECTRICAL CHARACTERISTICS (TCASE =25C UNLESS OTHERWISE SPECIFIED) ON/OFF Symbol V(BR)DSS IDSS IGSS VGS(th) RDS(on) Parameter Drain-source Breakdown Voltage Zero Gate Voltage Drain Current (VGS = 0) Gate-body Leakage Current (VDS = 0) Gate Threshold Voltage Static Drain-source On Resistance Test Conditions ID = 1 mA, VGS = 0 VDS = Max Rating VDS = Max Rating, TC = 125 C VGS = 20V VDS = VGS, ID = 50A VGS = 10V, ID = 4.5 A 3 3.75 0.36 Min. 300 1 50 10 4.5 0.4 Typ. Max. Unit V A A A V DYNAMIC Symbol gfs (1) Ciss Coss Crss Coss eq. (3) RG Parameter Forward Transconductance Input Capacitance Output Capacitance Reverse Transfer Capacitance Equivalent Output Capacitance Gate Input Resistance Test Conditions VDS = 10 V, ID = 4.5 A VDS = 25V, f = 1 MHz, VGS = 0 Min. Typ. 5.4 670 125 28 70 3.6 Max. Unit S pF pF pF pF VGS = 0V, VDS = 0V to 440 V f=1 MHz Gate DC Bias = 0 Test Signal Level = 20mV Open Drain Test Conditions VDD = 150 V, ID = 4.5 A RG = 4.7 VGS = 10 V (Resistive Load see, Figure 3) VDD = 240V, ID = 9 A, VGS = 10V Min. SWITCHING Symbol td(on) tr td(off) tf Qg Qgs Qgd Parameter Turn-on Delay Time Rise time Turn-off Delay Time Fall Time Total Gate Charge Gate-Source Charge Gate-Drain Charge Typ. 16 20 36 10 25 5.5 13.4 35 Max. Unit ns ns ns ns nC nC nC SOURCE DRAIN DIODE Symbol ISD ISDM (2) VSD (1) trr Qrr IRRM Parameter Source-drain Current Source-drain Current (pulsed) Forward On Voltage Reverse Recovery Time Reverse Recovery Charge Reverse Recovery Current ISD = 9 A, VGS = 0 ISD = 9 A, di/dt = 100A/s VDD = 40V, Tj = 150C (see test circuit, Figure 5) 165 0.9 11.2 Test Conditions Min. Typ. Max. 9 36 1.6 Unit A A V ns C A Note: 1. Pulsed: Pulse duration = 300 s, duty cycle 1.5 %. 2. Pulse width limited by safe operating area. 3. Coss eq. is defined as a constant equivalent capacitance giving the same charging time as Coss when VDS increases from 0 to 80% VDSS. 3/8 STL9NK30Z Output Characteristics Transfer Characteristics Transconductance Static Drain-source On Resistance Gate Charge vs Gate-source Voltage Capacitance Variations 4/8 STL9NK30Z Normalized Gate Thereshold Voltage vs Temp. Normalized On Resistance vs Temperature Source-drain Diode Forward Characteristics Normalized BVDSS vs Temperature 5/8 STL9NK30Z Fig. 1: Unclamped Inductive Load Test Circuit Fig. 2: Unclamped Inductive Waveform Fig. 3: Switching Times Test Circuit For Resistive Load Fig. 4: Gate Charge test Circuit Fig. 5: Test Circuit For Inductive Load Switching And Diode Recovery Times 6/8 STL9NK30Z PowerFLATTM(5x5) MECHANICAL DATA mm. MIN. A A1 b c D E E2 e 2.49 0.43 0.64 TYP 0.90 0.02 0.51 0.71 5.00 5.00 2.57 1.27 2.64 0.098 MAX. 1.00 0.05 0.58 0.79 0.017 0.025 MIN. inch TYP. 0.035 0.001 0.020 0.028 0.197 0.197 0.101 0.050 0.104 MAX. 0.039 0.002 0.023 0.031 DIM. 7/8 STL9NK30Z Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. (c) The ST logo is a registered trademark of STMicroelectronics (c) 2002 STMicroelectronics - Printed in Italy - All Rights Reserved STMicroelectronics GROUP OF COMPANIES Australia - Brazil - Canada - China - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan - Malaysia - Malta - Morocco Singapore - Spain - Sweden - Switzerland - United Kingdom - United States. (c) http://www.st.com 8/8 |
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